Functional Description

The xSil 248B is designed to connect an IDE/ATAPI device or Flash media to USB.  It features the following:

• 100-pin 16mm x 16mm QFP package

• Single chip with integrated USB 2.0 PHY

• Serial EEPROM port

• Supports up to 27 types of media. (Application notes available.)

• IDE/ ATAPI device support

• Supports On-board NAND as a storage device

• Firmware enhancements can be stored on On-board NAND when populated

• 115K Baud Serial port

• Two General Purpose Timers

• Watchdog Timer

• 16 bit Processor

• Programmable Read and Write widths

• Optimum hardware controlled transfer for speed and scalability

Packaging

The xSil 248B is a 100-pin QFP package. This device is available in lead free packaging.

USB Engine

The xSil 248B meets the Universal Serial Bus (USB) specification V2.0 and V1.1.

Serial EEPROM Port

The xSil 248B provides a serial interface to access external EEPROM's.  The interface is implemented using General Purpose I/O signals and can support a variety of serial EEPROM formats.

IDE/ ATAPI

The xSil 248B processor can be designed to interface to an IDE or ATAPI device. It supports PIO modes 0..5 of data transfer.

Serial port

Supports 7200 to 115.2K baud. Is useful as a debug port and can also be used to access the EEPROM for Reads / Writes from the serial port.

General Purpose Timers

Two general-purpose timers, Timer0 and Timer1 are provided to allow firmware programmers to keep track of timeouts as well as to generate delays.

Watchdog Timer

A Watchdog Timer (WT) is provided to enable catastrophic events to interrupt the processor. The Watchdog Timer overflow causes an internal processor reset. The Processor can read the WT bit after exiting reset to determine if the WT bit is set. If it is set, a watchdog timeout occurred. The timeout is selectable to any of the following values: 1 second, 4 seconds, 8 seconds or 16 seconds.

xSil 248B Processor

The xSil 248B Processor has a built-in 16-bit processor along with a BIOS ROM. The processor operates with a specialized instruction set optimized for Mass Storage applications and USB transaction processing. The start up code for the 16-bit processor resides in a masked ROM.

RAM Interface

The xSil 248B chip comes with an Internal RAM.  Data is transferred in EHS (Extra High Speed) mode to ensure optimum transfer speeds.

Masked ROM

The Masked ROM consists of  the xSil 248B processor start-up code and the functions listed below:

• Power On Initialization

• USB packet transaction management

• USB Power Management (S0..S3 modes)

• USB Enumeration Management

• API support for USB transactions, EEPROM Interface, Memory Management etc.

• Built-in Library functions for IDE/ ATAPI and Flash devices

The firmware is easily extended / expanded by using External Serial EEPROM.  The BIOS provides several services to facilitate this expansion code.  At boot-up time, the scan services of the BIOS search for the expansion signature in the Serial EEPROM as well as via the UART and USB. For more information, refer to Applications section of this manual.

The BIOS API functions are designed as Software Interrupts, making it easy for enhancements. Any Interrupt can be enhanced / modified by inserting the user defined function in the interrupt placeholder.  When this interrupt is called by the BIOS, the user defined function is called first to enhance the behavior before passing it on to the standard BIOS function?s call or return without passing it on.

Programmable Read and Write cycles

The external cycles to flash using the D[15:0], and SM[7:0] buses are software configurable.